Mastouille

Topaz 🐇OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at <a href="https://digitaljs.tilk.eu/" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://digitaljs.tilk.eu/</a> but you can also run it locally. <a href="https://oldbytes.space/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> <a href="https://oldbytes.space/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://oldbytes.space/tags/ulx3s" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#ulx3s</a>

Laurent FRANCOISEEt voici un début de carte vidéo en mode texte faite en <a href="https://piaille.fr/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> sur la carte <a href="https://piaille.fr/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> ICE40 d'Olimex. La résolution est de 640x200 en 8 couleurs avec une fonte 8x8 IBM EGA (tout ça est totalement arbitraire et peut être changé en modifiant le code en verilog !) Ce petit projet me permet de prendre en main la chaîne de développement (Yosys), complétée par Iverilog et GtkWave pour la simulation. Que des logiciels libres !

IT NewsThe Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - <a href="https://hackaday.com/2025/04/13/the-spade-hardware-description-language/" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://hackaday.com/2025/04/13/the-spade-hardware-description-language/</a> <a href="https://schleuss.online/tags/hardwaredescriptionlanguage" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hardwaredescriptionlanguage</a> <a href="https://schleuss.online/tags/spadelanguage" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#spadelanguage</a> <a href="https://schleuss.online/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hardware</a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> <a href="https://schleuss.online/tags/asic" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#asic</a> <a href="https://schleuss.online/tags/vhdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#vhdl</a> <a href="https://schleuss.online/tags/hdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hdl</a>

FLFDonc d'un coté quartus me chie des milliers de warnings pour des trucs à la con. Et quand j'essais d'écrire sur des port d'entrées, là aucun problème, pas d'erreur ....<a href="https://piaille.fr/tags/quartus" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#quartus</a> <a href="https://piaille.fr/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://piaille.fr/tags/input" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#input</a> <a href="https://piaille.fr/tags/assign" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#assign</a> <a href="https://piaille.fr/tags/agilex5" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#agilex5</a>

JackHey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.Technical work is often with <a href="https://recurse.social/tags/rust" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#rust</a> <a href="https://recurse.social/tags/kicad" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#kicad</a> <a href="https://recurse.social/tags/python" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#python</a> <a href="https://recurse.social/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://recurse.social/tags/c" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#c</a>, and in all-too-rare moments stuff like <a href="https://recurse.social/tags/haskell" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#haskell</a> <a href="https://recurse.social/tags/forth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#forth</a> <a href="https://recurse.social/tags/agda" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#agda</a> and <a href="https://recurse.social/tags/prolog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#prolog</a> I've never been much for social media, usually preferring to keep interests local: a better-detailed <a href="https://recurse.social/tags/introduction" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#introduction</a> to follow as I figure this out 🙂

PipelineCGifted a new <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a> dev board this season? 🤓 PipelineC aims to make <a href="https://fosstodon.org/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hardware</a> description easier for <a href="https://fosstodon.org/tags/embedded" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#embedded</a> folks. Check out the new getting start page. Happy to help you get going! <a href="https://fosstodon.org/tags/hdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hdl</a> <a href="https://fosstodon.org/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://fosstodon.org/tags/vhdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#vhdl</a> <a href="https://fosstodon.org/tags/hls" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hls</a> <a href="https://fosstodon.org/tags/HLS" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#HLS</a> <a href="https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup</a>

iantoToday's <a href="https://toot.wales/tags/AdventOfCode" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#AdventOfCode</a> part1 was again a surprisingly fast success (anonymous variables in <a href="https://toot.wales/tags/perl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#perl</a> ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (<a href="https://toot.wales/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a>), and will also have the 10yo learn how to solve it (<a href="https://toot.wales/tags/python" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#python</a>). Thanks a lot to <a href="https://hachyderm.io/@ericwastl" class="u-url mention" rel="nofollow noopener noreferrer" target="_blank">@ericwastl</a> for not ruining Sunday with a 3d falling grid problem!

FluxIs 2025 the year of <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a> on the desktop? 🤔 Please suggest interesting FPGA projects and people to inspire us for the year ahead. 🚀I'm working on a 2D graphics accelerator in <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> and <a href="https://mastodon.social/tags/riscv" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#riscv</a> assembler.

IT NewsDid You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - <a href="https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/</a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://schleuss.online/tags/yosys" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#yosys</a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> <a href="https://schleuss.online/tags/vhdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#vhdl</a>

iantoFirst steps completed on this years <a href="https://toot.wales/tags/AdventOfCode" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#AdventOfCode</a> pure-hardware challenge (no processor, no software) solution: behavioural <a href="https://toot.wales/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> that solves both parts of day 1. Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an <a href="https://toot.wales/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> ... but I am stupid enough to try.

Alfred M. SzmidtCalling all <a href="https://mastodon.social/tags/HDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#HDL</a> hackers! I need help in putting the <a href="https://mastodon.social/tags/MIT" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#MIT</a> <a href="https://mastodon.social/tags/CADR" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#CADR</a> onto a FPGA board. <a href="https://mastodon.social/tags/VHDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#VHDL</a>, <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a>, does not matter much. Who is up for a fun challange? <a href="https://mastodon.social/tags/LispMachine" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#LispMachine</a>

FluxThe <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a> source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: <a href="https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics</a>

Flux<a href="https://mastodon.social/tags/ULX3S" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#ULX3S</a> users are in a similar situation. You need the USRMCLK macro to access the SPI clock. Accessing the SPI clock on different dev boards is more time-consuming than writing the <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a> SPI module. 😅

FluxNow this looks like an interesting project: <a href="https://github.com/amaranth-lang/rtl-debugger" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://github.com/amaranth-lang/rtl-debugger</a>"VS Code based debugger for hardware designs in <a href="https://mastodon.social/tags/Amaranth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Amaranth</a> or <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a>" Can you tell us any more <a href="https://mastodon.social/@whitequark" class="u-url mention" rel="nofollow noopener noreferrer" target="_blank">@whitequark</a> ?

FluxI have updated my guide to <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a> Simulation with Verilator and SDL to cover Windows as well as Linux and macOS.If your Verilog project uses graphics, I can't recommend Verilator/SDL simulation highly enough. The turnaround time is *so* fast! <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a> ⏩ <a href="https://projectf.io/posts/verilog-sim-verilator-sdl/" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://projectf.io/posts/verilog-sim-verilator-sdl/</a>

FLFI asked <a href="https://piaille.fr/tags/ChatGPT" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#ChatGPT</a> to show me the diagram of a CLB contained in the <a href="https://piaille.fr/tags/CLEAR" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#CLEAR</a> and I got this :) Not exactly what I wanted, but beautiful draw ;) <a href="https://piaille.fr/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a> <a href="https://piaille.fr/tags/openfpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#openfpga</a> <a href="https://piaille.fr/tags/vpr" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#vpr</a> <a href="https://piaille.fr/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://piaille.fr/tags/clb" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#clb</a> <a href="https://piaille.fr/tags/ia" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#ia</a>

Amini AllightIs it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee an edge alignment or a phase shiftBoosts for visibility appreciated! <a href="https://mastodon.gamedev.place/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://mastodon.gamedev.place/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> <a href="https://mastodon.gamedev.place/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hardware</a> <a href="https://mastodon.gamedev.place/tags/openhardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#openhardware</a>

IT NewsTiny Tapeout 4: A PWM clone of Covox Speech Thing - Tiny Tapout is an interesting project, leveraging the power of cloud computing and... - <a href="https://hackaday.com/2024/06/21/tiny-tapeout-4-a-pwm-clone-of-covox-speech-thing/" rel="nofollow noopener noreferrer" translate="no" target="_blank">https://hackaday.com/2024/06/21/tiny-tapeout-4-a-pwm-clone-of-covox-speech-thing/</a> <a href="https://schleuss.online/tags/retrocomputing" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#retrocomputing</a> <a href="https://schleuss.online/tags/githubactions" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#githubactions</a> <a href="https://schleuss.online/tags/tinytapeout" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#tinytapeout</a> <a href="https://schleuss.online/tags/synthesis" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#synthesis</a> <a href="https://schleuss.online/tags/testbench" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#testbench</a> <a href="https://schleuss.online/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#hardware</a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#verilog</a> <a href="https://schleuss.online/tags/audio" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#audio</a> <a href="https://schleuss.online/tags/asic" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#asic</a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#fpga</a> <a href="https://schleuss.online/tags/dac" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#dac</a> <a href="https://schleuss.online/tags/pwm" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#pwm</a>

MecrispThe space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are <a href="https://chaos.social/tags/Assembler" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Assembler</a>, <a href="https://chaos.social/tags/Forth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Forth</a> and <a href="https://chaos.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a> on <a href="https://chaos.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a>. I am the author of <a href="https://chaos.social/tags/Mecrisp" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Mecrisp</a>, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with <a href="https://fosstodon.org/@BrunoLevy01" class="u-url mention" rel="nofollow noopener noreferrer" target="_blank">@BrunoLevy01</a> (<a href="https://chaos.social/tags/FemtoRV" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FemtoRV</a> Gracilis) and I love <a href="https://chaos.social/tags/sizecoding" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#sizecoding</a> challenges (Byte-Athlon Champion in <a href="https://chaos.social/tags/Lovebyte" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Lovebyte</a> 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

RemiWell after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough. But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.Anyhow I don't really know how far this might go, but if someone is looking for a <a href="https://universeodon.com/tags/EE" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#EE</a> with 25 years experience in digital design primarily with <a href="https://universeodon.com/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#FPGA</a> and <a href="https://universeodon.com/tags/VHDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#VHDL</a> (and a smattering of <a href="https://universeodon.com/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a>), including verification mainly using <a href="https://universeodon.com/tags/OSVVM" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#OSVVM</a> and <a href="https://universeodon.com/tags/UVVM" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#UVVM</a> (the latter modeled after <a href="https://universeodon.com/tags/UVM" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#UVM</a>) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

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