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#verilog
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En réponse à Cyber-Fox 
@postroutine I've used Verilator, and it works reasonably well given what it's trying to do. Terribly low-level, though. #fpga #verilog
Cooked up this abomination at ZuriHac 2025 -- execute Verilog circuits right from your Haskell! All the blame for the idea goes to @kmett https://mazzo.li/posts/inline-verilog.html
OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s
Et voici un début de carte vidéo en mode texte faite en #verilog sur la carte #fpga ICE40 d'Olimex.
La résolution est de 640x200 en 8 couleurs avec une fonte 8x8 IBM EGA (tout ça est totalement arbitraire et peut être changé en modifiant le code en verilog !)
Ce petit projet me permet de prendre en main la chaîne de développement (Yosys), complétée par Iverilog et GtkWave pour la simulation. Que des logiciels libres !
The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl
Hackaday · The Spade Hardware Description LanguageSpade is an open-source hardware description language (HDL) developed at Linköping University, Sweden. Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to de…
Donc d'un coté quartus me chie des milliers de warnings pour des trucs à la con. Et quand j'essais d'écrire sur des port d'entrées, là aucun problème, pas d'erreur ....
Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.
Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog
I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out 
PipelineC aims to make 
Today's #AdventOfCode part1 was again a surprisingly fast success (anonymous variables in #perl ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (#verilog), and will also have the 10yo learn how to solve it (#python). Thanks a lot to @ericwastl for not ruining Sunday with a 3d falling grid problem!
GIF
Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl
Hackaday · Did You Know YoSys Knows VHDL Too?We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write…
First steps completed on this years #AdventOfCode pure-hardware challenge (no processor, no software) solution: behavioural #verilog that solves both parts of day 1.
Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an #fpga ... but I am stupid enough to try.
Suite du fil
The #Verilog source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics
Suite du fil
Now this looks like an interesting project: https://github.com/amaranth-lang/rtl-debugger
"VS Code based debugger for hardware designs in #Amaranth or #Verilog"
Can you tell us any more @whitequark ?
GitHubGitHub - amaranth-lang/rtl-debugger: VS Code based debugger for hardware designs in Amaranth or VerilogVS Code based debugger for hardware designs in Amaranth or Verilog - amaranth-lang/rtl-debugger
I have updated my guide to #Verilog Simulation with Verilator and SDL to cover Windows as well as Linux and macOS.
If your Verilog project uses graphics, I can't recommend Verilator/SDL simulation highly enough. The turnaround time is *so* fast! #FPGA 
https://projectf.io/posts/verilog-sim-verilator-sdl/
Project F · Verilog Simulation with Verilator and SDLIt can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer.
