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#verilog

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OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

Et voici un début de carte vidéo en mode texte faite en #verilog sur la carte #fpga ICE40 d'Olimex.
La résolution est de 640x200 en 8 couleurs avec une fonte 8x8 IBM EGA (tout ça est totalement arbitraire et peut être changé en modifiant le code en verilog !)
Ce petit projet me permet de prendre en main la chaîne de développement (Yosys), complétée par Iverilog et GtkWave pour la simulation. Que des logiciels libres !

Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.

Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog

I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out 🙂

Today's #AdventOfCode part1 was again a surprisingly fast success (anonymous variables in #perl ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (#verilog), and will also have the 10yo learn how to solve it (#python). Thanks a lot to @ericwastl for not ruining Sunday with a 3d falling grid problem!

First steps completed on this years #AdventOfCode pure-hardware challenge (no processor, no software) solution: behavioural #verilog that solves both parts of day 1.
Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an #fpga ... but I am stupid enough to try.