It's an interesting point you highlight because I've never thought of things through that paradigm. Now that I see it, I realise I'm hoping to transition to #openBSD because I believe of mainstream operating systems, it probably has the best #DX.
In this particular case, I believe that the developers exploit that in order to optimise for what might be called #security which impresses me.
I realise it's probably an outlier in this regard!
Can We Replace a Program Counter with a Linear-Feedback Shift Register? Yes We Can! - Today we heard from [Richard James Howe] about his new CPU. This new 16-bit CPU is... - https://hackaday.com/2025/05/31/can-we-replace-a-program-counter-with-a-linear-feedback-shift-register-yes-we-can/ #forth #fpga #vhdl #cpu #vm
Hello,
Do you know where I can found a documentation about Tcl and VHDL in Info format ? (Or in a format I can convert to Info)
The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl
@flomaraninchi Ça peut également être qu'il ne faut pas mettre un point virgule à la fin de la ligne !
Quand on liste les ports d'entrées sorties ligne par ligne par exemple ;)
On combining #guix, #ghdl, #vunit and #sourcehut to perform #ci testing of digital electronic designgs in #vhdl for #fpga, using exclusively #freesoftware.
Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl
#ghdl (in its #clang variant), a #freesofware #vhdl analyzer, compiler, simulator and synthesizer, is part now of #guixscience channel. It may be used as any other #guix package with a simple
guix install ghdl-clang
This means too that pre-built substitutes are available online.
#ci testing of a #vhdl project in the #sourcehut build farm.
It runs a #ghdl simulation using the #osvvm verification library, creating a #guix local profile from a manifest file to handle all dependencies. Requirements are pulled from a custom repository. All #reproductible thanks to pinned guix channels.
#openlogic, a #vhdl stdlib library of commonly used components, reusable and vendor/tool-independent, is available now with #guix, using a home made channel. Enjoy !
#Reproductibilité des résultats de #recherche à l’aide de #GNU / #Guix.
Avec application à la gestion de bibliothèques matérielles.
https://webcast.in2p3.fr/video/reproducibilite-des-resultats-de-recherche-a-laide-de-gnu-guix
Making USB Blaster Clones Work For Linux - The last time we checked in with [Downtown Doug Brown], he had some cheap Altera U... - https://hackaday.com/2024/07/29/making-usb-blaster-clones-work-for-linux/ #alterablaster #fpga #cpld #vhdl
There seems to be an early stage of a #Commodore #VIC20 core for the #MEGA65. I don’t know how to build a .cor file from this repository. Can someone please provide some insight on how this works?
Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.
But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.
Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).
(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)
@cstanhope @stman wow, I was not expecting this result! Looks like this one dude got pretty damn far in implementing #Wasm in #VHDL for the CMOD A7-35T evaluation board:
https://github.com/denisvasilik/wasm-fpga-cmod-a7-35t
It's apparently abandoned for 3 years now. Why did he stop? What insights does this legendary hacker hold? 
PipelineC aims to make 
